a

sub extract_verilog_file_data

{

 my %TMP;

 my $file = shift(@_);

 open( my $IN, $file ) || die("Can't open Verilog file ($file) for read. Program Terminated!\n");

 while (!eof($IN))

 {

   my $line = <$IN>;

   if ( $line =~ /^\s*(\S+)\s+   ### cell name

                   (\S+)\s*     ### inst name

                   \(\s*\.

                   /x )

   {

     my $cell = $1;

     my $inst = $2;

     $inst =~ s/\\//;

     $TMP{$inst} = $cell;

   } # if

 } # while

 close($IN);

 return(%TMP);

} # extract_verilog_file_data

test

farklor